1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and a semiconductor device.
2. Description of the Related Art
A CPU (Central Processing Unit) and a logic device including a CPU core are composed of a logic circuit section formed mainly by various logic gates and a memory circuit section such as a shift register, a cache memory and the like. This memory circuit section is formed by an SRAM (Static Random Access Memory), for example.
The performance of a logic gate or an SRAM is determined by the performance of a MOS (Metal Oxide Semiconductor) transistor forming the logic gate or the SRAM.
The performance of an MOS transistor is given by the following Equation (1) expressing a drain-to-source current and Equation (2) expressing variation σVt in threshold voltage (see “Fundamentals of Modern VLSI Devices” by Taur and Ning, p. 279).Ids=β(Vgs−Vt)2/2  (1)σVt=q√(Na·Wdm0/(3LW))/Cox  (2)
In the above Equation (1) and Equation (2), β=μ·W/L, where μ is mobility, L is the gate length of the transistor, and W is the gate width of the transistor, Na is a channel impurity concentration, Wdm0 is the width of a channel depletion layer, and Cox is a gate capacitance.
Generally, the threshold voltage Vt cannot be set at about 0.2 V or lower in a large-scale device due to limitation of a leakage current. Therefore, when Vgs becomes lower than 1.0 V and transistor size (L·W) is reduced according to a scaling law, variation in Ids (performance) is sharply increased.
Accordingly, a provision is made by setting a large operation margin reflecting the increased variation in device design.
There is a static noise margin (hereinafter referred to as an SNM) shown in FIG. 9 as an index indicating the operation margin of an SRAM cell.
In addition, as shown in FIG. 10, the SNM of an SRAM cell formed by six transistors and a variation σSNM in SNM are determined by four transistors MnL, MnR, MpL, and MpR. The transistors MnL and MnR are N-channel transistors, and the transistors MpL and MpR are P-channel transistors. That is, the variation σSNM is expressed by the following Equation (3).ρSNM=σVth√{(∂SNMnR/∂VtnR)2+(∂SNMnL/∂VtnL)2+(∂SNMpR/∂VtpR)2+(∂SNMpL/∂VtpL)2}  (3)
In Equation (3), each term of the square root indicates sensitivity of the SNM to Vt variation of each of the four transistors (see ITRS, PIDS WG reports in 2004, for example). Incidentally, the SNMs of the four transistors MnL, MnR, MpL, and MpR are set as SNMnL, SNMnR, SNMpL, and SNMpR, respectively. Incidentally, Vt and Vth denote a threshold voltage, and a threshold voltage is described herein as Vt or Vth according to the description of the quoted document.
It is understood that when σVth is increased by scaling, σSNM is increased, SNM is reduced, and the percent defective of the SRAM is increased sharply.
Measures against this are the following four items. (a) Voltage is not lowered (Vdd, in particular, is not lowered). (b) The thickness of a gate oxide film is reduced (Cox is increased, and thus σVth is reduced). (c) A fully depleted transistor is employed as SRAM transistor (Na is reduced). (d) A redundant array is prepared for a defective SRAM cell, and a yield is ensured by changing to the redundant array.
The (a) item lowers only the voltages of a word line WL and a bit line BL without lowering Vdd, as shown in FIG. 10, and thus enables operation with low power consumption without reducing SNM. The (b) item uses the following thin film formed by a metal-organic chemical vapor deposition
(MOCVD) method or an atomic layer deposition (ALD) method as a gate insulating film. A hafnium oxide (HfO2), a hafnium silicide oxynitride (HfSiON), a zirconium oxide (ZrO2), or a zirconium silicide oxynitride (ZrSiON) is used. A titanium nitride (TiN), a tantalum carbide (TaC), tungsten (W) or the like is used as gate electrode. Such methods are proposed. Further, as the (c) item, use of a FinFET type transistor as shown in FIG. 11A or a fully depleted SOI (silicon-on-insulator) transistor having a thin Si layer as shown in FIG. 11B as SRAM transistor is proposed.
As scaling advances, a total number of impurities included in the channel of the transistor is reduced, and variation in threshold voltage due to impurity variation is inevitably increased.
However, in a logic circuit, setting a wide operation margin in consideration of the variation causes a decrease in operating speed, and increasing the power supply voltage Vdd to compensate for the decrease in operating speed invites an increase in power consumption.
In addition, an increase in variation in threshold voltage as described above proportionally increases the SNM variation of the SRAM, and also increases the percent defective of the SRAM. Thus, when this is remedied by a redundant cell and a redundant circuit, the ratio of a redundant array is increased with scaling, and the area of the SRAM as a whole is increased. In addition, scaling only size and not lowering power supply voltage invites an increase in electric field, an increase in leakage current, and an increase in power consumption. Further, reducing the thickness of a gate oxide film using a high dielectric constant (High-k) film and a metallic gate theoretically reduces variation in SNM and enables lower voltage, but eventually invites an increase in SNM variation because Na is increased with scaling.
On the other hand, a fully depleted transistor makes it possible to make Na extremely low, and has a potential for greatly decreasing threshold voltage and SNM variation. However, the FinFET has a vertical transistor structure, so that minute gate electrode processing, ion implantation, diffusion layer formation, side wall spacer formation, and salicide formation are difficult. There is another problem of a high contact resistance because a contact is connected only at a thin Si terminal. Further, a thin SOI transistor (UTSOI) has a high parasitic resistance, and is increased in threshold voltage due to variation in silicon film thickness.